Understanding RISC-V and Its Potential Impact on the Wearables Industry

Within smartphones and various other devices, a pivotal component is the System on a Chip (SoC), often referred to more broadly as a “processor” or CPU in the context of personal computers. Over time, there has been remarkable progress in instruction set architectures, encompassing both CISC and RISC instruction sets used by industry giants like Intel/AMD and ARM, respectively. However, a relatively new contender, RISC-V (founded in 2010), has emerged and is gaining significance. This technology has substantial implications not only for Android and WearOS but also for major players such as Qualcomm and other investors.

Exploring RISC-V: A New Open-Source CPU Architecture

RISC-V, pronounced “risk five,” stands as an Instruction Set Architecture (ISA), akin to ARM and RISC. However, what sets it apart is that it is entirely devoid of licensing constraints and is open-source. To illustrate, think of an instruction set architecture as a bridge that connects hardware and software. It establishes the rules and procedures governing the interplay between hardware and software to produce desired outcomes whether it’s a simple UI button press or the execution of intricate instructions during a gaming session.

The RISC-V ISA stands out for its adaptability and efficiency. A key incentive for companies to invest in RISC-V is its open-source nature, relieving them of any obligation to pay licensing fees.

While the name “RISC-V” might suggest it as a successor to RISC, this is not the case. RISC is a proprietary architecture employed by ARM to provide instructions to companies like Samsung, Qualcomm, and Apple, which then utilize these “instructions” to design their own System on Chips (SoCs). In contrast, RISC-V eliminates intermediaries. It operates as a free and open-source framework, enabling companies to access the instructions without the burden of substantial licensing fees associated with ARM. This independence empowers them to construct processors based on the RISC-V ISA.

RISC-V International continually seeks to enhance the open-source ISA, much like the development of open-source software. It’s important to note that while RISC-V is license-free, companies have the option to take it and create closed-source implementations if they choose to do so. This is somewhat analogous to the situation with Android, where the Android Open Source Project (AOSP) is completely free (although Google does charge OEMs for licensing Google Apps). Companies can build on AOSP and develop their own user interfaces without disclosing the source code.


RISC, RISC-V, and CISC are all different types of instruction set architectures used in various computing devices. RISC and RISC-V are Reduced Instruction Set Computers, with RISC-V being open-source and free, while RISC is proprietary. CISC, on the other hand, stands for Complex Instruction Set Computer and is used by processor manufacturers like Intel and AMD.

The key distinction between these architectures lies in how instructions are processed. In CISC, the instruction set completes complex instructions to perform tasks, while in RISC, the instruction set focuses on executing a large number of simple instructions to accomplish a task. RISC-V, as an open-source alternative to RISC, offers flexibility and efficiency to companies without the need for licensing fees.

CISC architecture is exemplified by processors such as Intel’s x86 and x86-64. These processors, known for their power and capabilities, have been widely used in personal computers and various industries. While they are powerful, they tend to require more power and are not as efficient as RISC architecture. In recent years, the line between RISC and CISC has blurred, with RISC architecture gaining ground, as demonstrated by Apple’s M1 processors and their increased efficiency and performance.

The Advantages of RISC-V: Why It Matters for Wearables

Indeed, the cost-saving nature of RISC-V, with its free and open-source characteristics, is a significant advantage for companies like Google and Qualcomm. It eliminates the need to pay licensing fees and fosters innovation. Moreover, there are several advantages for consumers and manufacturers.

  • RISC-V offers enhanced security through rapid open-source security flaw mitigation.
  • It facilitates smoother software updates due to its common ISA shared across manufacturers.
  • The open-source environment fosters accelerated development and efficiency, resulting in improved SoC performance.

Another compelling reason for embracing RISC-V is to counter ARM’s monopoly and looming licensing challenges. ARM has been escalating its licensing fees, leaving manufacturers with limited alternatives. The attempted acquisition of ARM by NVIDIA raised concerns within the industry, as it could have resulted in restricted access to the ARM ISA for other companies. To safeguard their interests, companies began investing in RISC-V’s development, injecting financial support and instigating hardware advancements to drive the next wave of connected platforms.

RISC-V also addresses a critical issue related to trade barriers. Recent events in the tech industry, such as the US banning Huawei and China’s retaliatory actions, have highlighted the importance of a non-restricted ISA. RISC-V, being both license-free and based in Switzerland, ensures freedom from trade impediments and extraterritorial control by any single country.

How Will Google and Qualcomm Benefit from RISC-V?

Well, it brings several significant changes. First and foremost, Qualcomm stands to benefit from substantial cost savings as it transitions to RISC-V across all its product categories, including smartphones, IoT devices, and other connected technologies. Additionally, Qualcomm is teaming up with Google to develop RISC-V-based processors for Google’s wearable devices, like the Pixel Watch and Fitbit. These processors could potentially find their way into future Pixel smartphones as well, replacing the current Tensor SoC. Initial implementation is expected in Google’s Fitbit products.

Earlier this week, Google shared an update about its efforts to bring Android to RISC-V. The company is working on adapting its WearOS and other platforms to run on RISC-V processors. In a video shared in the post, Android was seen booting up and running on a RISC-V processor. While the Android Open Source Project (AOSP) isn’t fully optimized for RISC-V yet, Google has announced its plans to make emulators available for public use by 2024. This move signifies a significant step toward RISC-V adoption and compatibility within the Android ecosystem.

The advantages of RISC-V present an opportunity for Google to enhance its wearables, push more frequent updates, and potentially improve overall performance and battery life. While initial RISC-V vs. RISC test results look promising, it’s important to note that RISC-V is still in its early stages of development and optimization. With continued investment and development, it has the potential to become a compelling choice for future wearable devices and other connected platforms.

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